Dynamic Power Suppression Technique in Booth Multipliers
The SPST has been applied on both the modified booth decoder and the compression tree of multipliers to enlarge the power reduction. In this paper, the authors provide the experience of applying an advanced version of the authors' former Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the use-less switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition.
Provided by: International Journal of Innovative Technology and Exploring Engineering (IJITEE) Topic: Hardware Date Added: Sep 2012 Format: PDF