Institute of Electrical & Electronic Engineers
The phenomenon of digital convergence and increasing application complexity today is motivating the design of Chip Multi-Processor (CMP) applications with multiple use cases. Most traditional on-chip communication architecture design techniques perform synthesis and optimization only for a single use-case, which may lead to sub-optimal design decisions for multi-use case applications. In this paper, they present a framework to generate a dynamically reconfigurable crossbar-based on-chip communication architecture that can support multiple use-case bandwidth and latency constraints. Their framework generates on-chip communication architectures with a low cost, low power dissipation, and with minimal reconfiguration overhead.