Dynamically Reconfigurable Register File for a Softcore VLIW Processor

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Provided by: edaa
Topic: Hardware
Format: PDF
In this paper, the authors present dynamic reconfiguration of a register file of a Very Long Instruction Word (VLIW) processor implemented on an FPGA. They developed an open-source reconfigurable and parameterizable VLIW processor core based on the VLIW EXample (VEX) Instruction Set Architecture (ISA), capable of supporting reconfigurable operations as well. The VEX architecture supports up to 64 multiported shared registers in a register file for a single cluster VLIW processor. This register file accounts for a considerable amount of area in terms of slices when the VLIW processor is implemented on an FPGA.
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