Effect of Gate Dielectric on Threshold Voltage of Nanoscale MOSFETS

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Provided by: International Journal of Engineering Research and Development (IJERD)
Topic: Hardware
Format: PDF
An Integrated Circuit (IC) dimensions continue to decrease, RC delay, crosstalk noise, and power dissipation of the interconnect structure become limiting factors for ultra-large-scale integration of integrated circuits. Modern microcircuits may have eight metal layers, each separated by only 0.1 micrometers. RC delays and cross talk rather than transistor speed are now the major performance limitations. The semi-conductor industry has responded by developing copper metallization to replace aluminum and lower dielectric constant materials to replace silicon-oxide.
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