Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology Using N-Curve

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
The leakage power, performance, data retention and stability are the key challenges in Static Random Access Memory (SRAM) at Deep Sub-Micron (DSM) CMOS technology. In the DSM technology, when threshold voltage, channel length and gate oxide thickness are reduced, leakage currents in deep sub-micrometer regimes causes power dissipation in CMOS digital circuits which may affect the data ability and stability in the SRAM. In this paper, the effect of supply voltage has been observed in the IP3 SRAM bit-cell using N-curve methodology at the Room Temperature (RT).

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