Effective BIST Architecture to Reduce Hardware Overhead in Digital Circuits
In VLSI testing technology the role of DFT is inevitable to reduce hardware overhead and latency. Input vector monitoring Built In Self Test (BIST) architecture executes the testing of normal operating circuit without enforces the circuit offline. In this paper, to achieve goals that area overhead (number of gates) and Concurrent Test Latency (CTL) i.e., amount of time taken to complete testing the circuit. The relative locations from examined window can be stored in SRAM which can consume less power. The proposed effective BIST architecture is shown as better than other BIST schemes which result in terms of low area overhead and CTL.