Effective Management of DRAM Bandwidth in Multicore Processors

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Provided by: Purdue Federal Credit Union
Topic: Storage
Format: PDF
The two technology trends of increasing transistors per die and limited power budgets have driven every major processor vendor to multicore architectures. Technology trends are leading to increasing number of cores on chip. All these cores inherently share the DRAM bandwidth. The on-chip cache resources are limited and in many situations, cannot hold the working set of the threads running on all these cores. This situation makes DRAM bandwidth a critical shared resource. Existing DRAM bandwidth management schemes provide support for enforcing bandwidth shares but have problems like starvation, complexity, and unpredictable DRAM access latency.
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