International Journal for Science and Emerging Technologies with Latest Trends (IJSETT)
Signal integrity for high speed DDR memory design at the Printed Circuit Board (PCB) level is very essential and important for making a robust design. This paper describes how simulation tools can be helpful for choosing best termination method and other signal integration parameter along with the design process. A Simulation tool Hyperlynx has been used for high speed digital design for DDR2 in this paper. The author's present DDR 2 design example in which the main approach is to get wide opened eye with minimum level of overshoot and undershoot.