Efficient Approaches for Designing Fault Tolerant Reversible BCD Adders

Provided by: Binary Information Press
Topic: Hardware
Format: PDF
Reversible circuits are emerging as a promising technology for power minimization, CMOS design, digital signal processing, etc. One of the important issues in reversible logic is fault tolerant. Therefore, this paper presents the more efficient approaches for designing fault tolerant reversible fast BCD adders, which are carry-skip BCD adder and carry look-ahead BCD adder, designed using some basic building block including F2PG (Five variables Parity Preserving Gate) and MNFT (Modified New Fault Tolerant gate). These adders allow any fault that affects no more than a single signal readily detectable at the circuit primary outputs.

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