International Journals of Advanced Information Science and Technology (IJAIST)
Viterbi algorithm is widely used as a decoding technique for convolutional codes as well as a bit detection method in storage devices. The design space for VLSI implementation of Viterbi decoders is huge, involving choices of throughput, latency, area, and power. This Paper propose Fast ACS architecture to reduce the area and power of the ACS unit in Viterbi decoder. With the proposed structure it is possible to reduce the area and power of the ACS unit by 30% to 40% compare to conventional ACS architecture. The results are based on real designs for which actual synthesis and layouts are obtained using synopsys.