Now-a-days, Integrated Circuits (ICs), is becoming increasingly important as designs become more and more complicated. It is important to achieve a high level of reliability with minimum cost and time. This paper deals with reduced hardware for eliminating branch penalty cycles in pipelined processor. Generally control hazard causes a greater performance loss in pipelined processor such as MIPS. Here, the authors present improved pipelined processor architecture as well as eliminating branch and jump penalty. In the proposed architecture the number of multiplexers and adders were reduced compared to previously implemented architecture. The proposed architecture is implemented in Xilinx 10.1 tool using Verilog.