Efficient Area and Speed Optimized Multiplication Technique Using Vedic and Tree Addition Structure

Provided by: Advances in Computer Science : an International Journal (ACSIJ)
Topic: Hardware
Format: PDF
Now-a-days, the authors are living in digital world, where all the operations get performed more reliably and with highest accuracy by digital signal processor. The multiplier is the key element of all these processor like microprocessor, microcontroller, DSP processor, etc. After thorough study and deep analysis work, they have seen that the existing Vedic multiplication hardware has some limitation in terms of area. To overcome these limitations a novel approach has been proposed to design the Vedic multiplier with unique addition structure, which is used to add partially generated products.

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