Efficient Buffering and Scheduling for a Single-Chip Crosspoint-Queued Switch

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
The single-chip Crosspoint-Queued (CQ) switch is a compact switching architecture that has all its buffers placed at the cross points of input and output lines. Scheduling is also performed inside the switching core, and does not rely on latency-limited communications with input or output line-cards. Compared with other legacy switching architectures, the CQ switch has the advantages of high throughput, minimal delay, low scheduling complexity, and no speedup requirement. However, the cross point buffers are small and segregated, thus how to efficiently use the buffers and avoid packet drops remains a major problem that needs to be addressed.

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