Institute of Electrical & Electronic Engineers
The authors propose a floating - point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in these devices. They propose a format that reduces the variable shifter penalty. It is based on a radix - 64 representation such that the number of the possible shifts is considerably reduced. Thus, the execution time of the floating - point addition is highly optimized when it is performed in an FPGA device, which compensates for the multiplication penalty when a high radix is used, as experimental results have shown.