International Journal of Engineering Research and Applications (IJERA)
In this paper, the authors present a high speed binary floating point multiplier based on hybrid method. To improve speed multiplication of mantissa is done using hybrid method replacing existing multipliers like carry save multiplier, Dadda multiplier and modified booth multiplier. Hybrid method is a combination of Dadda multiplier and modified radix-8 booth multiplier. The design achieves high speed with maximum frequency of 555MHz compared to existing floating point multipliers. The multiplier implemented in Verilog HDL and analyzed in Quartus II 10.0 version.