Efficient Implementation of Reconfigurable MIMO Decoder Accelerator Chip
In this paper, the author present an energy efficient reconfigurable MIMO (Multiple Input Multiple Output) decoder accelerator hardware architecture. It delivers full programmability across different wireless standards (i.e., Wi-Fi, 3G-long term evolution and WiMAX) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. The authors propose a Hough transform architecture instead of CORDIC for the rotation unit in the processing core. The energy efficiency of their MIMO accelerator chip was compared against existing programmable MIMO accelerator, it delivered energy efficiencies that were 5% less than the existing system.
Provided by: International Journal of Innovative Research in Science, Engineering and Technology (IJIRSET) Topic: Mobility Date Added: Apr 2014 Format: PDF