Efficient On-line Interconnect Testing in FPGAs with Provable Detectability for Multiple Faults

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Provided by: edaa
Format: PDF
The authors present a very effective on-line interconnect Built-In-Self-Test (BIST) method I-BIST for FPGAs that uses a combination of the following novel techniques: a track-adjacent and a switch-adjacent (also called \"Mirror adjacent\") pairwise net comparison mechanism that achieves high detectability, a carefully designed set of only five net-configurations that cover all types and locations of wire-segment and switch faults, a 2-phase global-detailed testing approach, and a divide-and-conquer technique used in detailed testing to quickly narrow down the set of potential suspect interconnects that are then detail-diagnosed.
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