Efficient Pairwise Statistical Significance Estimation using FPGAs

Download Now
Provided by: Northwestern University
Topic: Hardware
Format: PDF
In this paper, the authors present a fast pairwise statistical significance estimator using a Field Programmable Gate Array (FPGA) coprocessor. The running time of the pairwise statistical significance estimation routine is dominated by the hundreds of local alignments it must compute. By offloading the alignment task to an accelerator designed to concurrently process multiple independent alignments, they are able to increase the end-to-end performance of the algorithm by more than 200x over a baseline software implementation.
Download Now

Find By Topic