Provided by: University of Munster
Date Added: Jul 2012
Coherence in a System-on-Chip (SoC) introduces complexity and overhead (snooping caches/directory, state bits, invalidations, etc.) in exchange for a clean and uniform shared memory model. As it is typical today, a SoC comprises a variety of cores with local caches, accelerators with local memories, and some form of shared Last-Level Cache (LLC), all interconnected with shared buses. The authors propose a very simple coherence protocol, fit for this environment, that eliminates L1 snooping and its associated complexity and costs.