Efficient Sparse Matrix-Vector Multiplication on x86-Based Many-Core Processors

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Sparse Matrix-Vector multiplication (SpMV) is an important kernel in many scientific applications and is known to be memory bandwidth limited. On modern processors with wide SIMD and large numbers of cores, the authors identify and address several bottlenecks which may limit performance even before memory bandwidth: low SIMD efficiency due to sparsity, overhead due to irregular memory accesses and load-imbalance due to non-uniform matrix structures. They describe an efficient implementation of SpMV on the Intel Xeon Phi Coprocessor, codenamed KNights Corner (KNC) that addresses the above challenges.
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