Provided by: Institute of Electrical & Electronic Engineers
Date Added: Oct 2006
In this paper, the authors investigate optimized synchronization techniques for shared memory on-Chip Multi-Processors (CMPs) based on Network-on-Chip (NoC) and targeted at future mobile systems. The proposed solution is based on the idea of locally performing synchronization operations requiring continuous polling of a shared variable, thus, featuring large contentions (e.g., spin locks and barriers). A HardWare (HW) module, the Synchronization-operation Buffer (SB), has been introduced to queue and to manage the requests issued by the processors.