International Journal of Advanced Research in Computer Science & Technology (IJARCST)
Digital circuit's complexity and density are increasing while, at the same time, more quality and reliability are required. These trends, together with high test cost, make the validation of VLSI circuits more and more difficult. This paper proposes a novel Test Pattern Generator (TPG) for built-in self-test. The authors' method generates Multiple Single Input Change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. According to the different scenarios of scan length, this paper develops two kinds of SIC generators to generate Johnson vectors and Johnson code word's i.e., the reconfigurable Johnson counter and the scalable SIC counter.