Efficient Timing Recovery Technique for Software Defined Radio Receiver using FPGA

Provided by: International Journal of Engineering and Advanced Technology (IJEAT)
Topic: Software
Format: PDF
In this paper, the authors present the timing recovery in software defined radio receiver as a widely used technique now-a-days. Software Defined Radios (SDR) is the more configurable hardware platforms that provide the technology for realizing the fast growing third and new generation digital wireless communication structure. The more complex duty performed in a high data rate wireless system is the synchronization. The timing synchronization in SDRs using FPGA based signal processors is introduced. The 16-QAM loop for performing coherent demodulation were described and reported on the suggestion of FPGA automation. A matched filter control system is used to provide and addressed the symbol timing recovery technique.

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