Efficient Translation of Algorithmic Kernels on Large-Scale Multi-Cores

Provided by: Iowa State University
Topic: Hardware
Format: PDF
In this paper the authors present the design of a novel embedded processor architecture (which they call a core) that makes use of a reconfigurable ALU. This core serves as the basis of custom 2-dimensional array architectures that can be used to accelerate algorithms such as cryptography and image processing. An efficient translation and mapping of instructions from the multi-core grid to the individual processor cores is proposed and illustrated with an implementation of the AES encryption algorithm on custom-sized grids.

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