Efficiently Tolerating Timing Violations in Pipelined Microprocessors

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the performance overhead of tolerating these faults. In this paper, the authors explore several techniques for optimizing instruction scheduling in an out-of-order pipeline, exploiting this new perspective in robust system design. Compared to recently proposed stall based techniques for tolerating predictable timing violations, they demonstrate a massive reduction in performance overhead, while supporting correct execution in faulty environments (64 - 97% across different benchmarks).

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