Eliminate Glitch Power Consumption at P.D Stage in CMOS Circuits
Glitch compensation method is proposed in this paper, which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed system can be seamlessly integrated to existing physical design flow. This paper includes the 10T full adder with transmission gate in which transmission gate is used as a compensation circuit which reduces the glitches. By adopting the proposed system the glitch power which is one of the major contributing factors for both dynamic and IR drop can be effectively reduced with less overhead and minimum impact on the existing flow.