Embedded Way Prediction for Last-Level Caches

Provided by: University of Miami School of Business Administration
Topic: Hardware
Format: PDF
In this paper, the authors investigate embedded way prediction for large Last-Level Caches (LLCs): an architecture and circuit design to provide the latency of parallel tag-data access at substantial energy savings. Existing way prediction approaches for L1 caches are compromised by the high associativity and filtered temporal locality of LLCs. They demonstrate: the need for wide partial tag comparison, which they implement with a dynamic CAM alongside the data sub-array wordline decode and the inhibit bit, an architectural innovation to provide accurate predictions when the partial tag comparison is inconclusive.

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