Empirical Design Bugs Prediction for Verification

Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-Under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, the authors propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon Artificial Neural Networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information.

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