Energy and Latency Aware Application Mapping Algorithm & Optimization for Homogeneous 3d Network on Chip

Provided by: Cornell University
Topic: Hardware
Format: PDF
Energy efficiency is one of the most critical issues in design of System on Chip. In Network-on-Chip (NoC) based system, energy consumption is influenced dramatically by mapping of Intellectual Property (IP) which affect the performance of the system. In this paper, the authors test the antecedently extant proposed algorithms and introduced a new energy proficient algorithm stand for 3D NoC architecture. In addition a hybrid method has also been implemented using bio-inspired optimization (particle swarm optimization) technique. The proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life application such as MMS, Telecom and VOPD.

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