Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems

Provided by: Brown University
Topic: Storage
Format: PDF
The authors propose a new design for an energy-efficient Hardware Transactional Memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a small, fully-associative transactional cache at the same level as the L1 cache. They propose an alternative design that unifies the transactional and L1 caches, and provides a small victim cache to reduce effects of capacity and conflict evictions. They evaluate their new HTM scheme on a variety of benchmarks, both in terms of energy and performance.

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