Institute of Electrical and Electronics Engineers
Energy-efficient design requires exploration of available algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this paper, methodology for energy-efficient design applied to 64-bit adders implemented with static CMOS, dynamic CMOS and CMOS compound domino logic families, is presented. The authors also examined 65nm, 45nm, 32nm and 22nm technology nodes to explore the applicability of the results in deep submicron technologies. By applying energy-delay tradeoffs on various levels, they developed adder topology yielding up to 20% performance improvement and 4.5 energy reduction over existing designs.