Association for Computing Machinery
Sub-threshold circuit design has become a popular approach for building energy efficient digital circuits. One drawback is performance degradation due to the exponentially reduced driving current. This had limited sub-threshold circuits to relatively low performance applications such as sensor networks. To retain the excellent energy efficiency while reducing performance loss, the authors propose to apply sub-threshold and near-threshold techniques to chip multi-processors. They show that an architecture where several slower cores are clustered together with a shared faster L1 cache is optimal for energy efficiency, because processor cores and memory operate best at different supply and threshold voltages.