International Journal of Engineering and Advanced Technology (IJEAT)
In this paper the authors present a technique to improve the over-all performance of the multiprocessor chip. Efficient partitioning of last-level cache memory in a multi-processor chip can increase the performance significantly. The concept is to first allocate the fixed number of ways for a core and then forced the cache data to be way aligned so that a particular way is owned by a core at a particular time. At the time of access, cores cooperate with each other to migrate the ways between them so that a core has to consult only those ways which it has owns to find its data from which dynamic energy can be saved and unused ways can be power-gated for saving the static energy.