Journal of Semiconductor Technology and Science (JSTS)
In the recent research, charge recovery logic is restudied because of its low power dissipation. In numerous presented literatures. This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS Boost Logic (pNBL), to achieve high speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed processing engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed.