Energy Minimum Operation in a Reconfigurable Gate-level Pipelined and Power-Gated Self Synchronous FPGA

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Provided by: University of Tokushima
Topic: Hardware
Format: PDF
A 65nm Self Synchronous Field Programmable Gate Array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. The authors show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in Power-Delay Product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process they are able to show up to 84.6x PDP improvement.
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