Association for Computing Machinery
Power consumption has become a major constraint in the design of processors today. To optimize a processor for energy-efficiency requires an examination of energy-performance tradeoffs in all aspects of the processor design space, including both architectural and circuit design choices. In this paper, the authors apply an integrated architecture-circuit optimization framework to map out energy-performance trade-offs of several different high-level processor architectures. They show how the joint architecture-circuit space provides a trade-off range of approximately 6.5x in performance for 4x energy, and they identify the optimal architectures for different design objectives.