Enhancing FPGA Performance for Arithmetic Circuits

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
The Field Programmable Gate Array (FPGA) is an attractive platform for hardware design due to its flexibility. FPGAs are often used for low-volume circuits that could not be profitably synthesized as an Application Specific Integrated Circuit (ASIC). FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To address this issue, this paper introduces a novel reconfigurable lattice built from counters rather than Look-Up Tables (LUTs) that can effectively accelerate the arithmetic portions of a circuit. The authors intend to integrate this novel lattice onto the same die as an FPGA.

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