The fixed-width multiplier is well attractive to many multimedia and digital signal processing systems. It proposes a reduction of truncation error from 16-bit to 8-bit MSB bits (truncated output) using simple error reduction circuit. The fixed width modified booth multiplier is used to minimize the partial product matrix of Booth multiplication. Multiplication is binary mathematical operation scaling one number by another. Lead the design of high accuracy, low power and area in MAC unit and compare with the Wallace tree multiplier.