Error Resilience of Intra-Die and Inter-Die Communication With 3D Spidergon STNoC

Provided by: edaa
Topic: Hardware
Format: PDF
Scaling down in Very Deep Sub-Micron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high performance integrated circuits wires become the performance bottleneck and the authors are shifting towards communication centric design paradigms. Networks-on-chip and stacked 3D integration are two emerging technologies that alleviate the performance difficulties of on-chip interconnects in nano-scale designs. In this paper, they present a design-time configurable error correction scheme integrated at link-level in the 3D Spidergon STNoC onchip communication platform.

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