Evaluating the Effects of Cache Redundancy on Profit

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Provided by: Northwestern University
Topic: Storage
Format: PDF
Previous papers in computer architecture have mostly neglected revenue and/or profit, key factors driving any design decision. In this paper, the authors evaluate architectural techniques to optimize for revenue/profit. The continual trend of technology scaling and sub-wavelength lithography has caused transistor feature sizes to shrink into the nanoscale range. As a result, the effects of process variations on critical path delay and chip yields have amplified. A common concept to remedy the effects of variations is speed-binning, by which chips from a single batch are rated by a discrete range of frequencies and sold at different prices.
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