Evaluating the Self-Optimization Process of the Adaptive Memory Management Architecture Self-aware Memory

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Provided by: Karlsruhe Institute of Technology (KIT)
Topic: Hardware
Format: PDF
With the continuously increasing integration level, manycore processor systems are likely to be the coming system structure not only in HPC but also for desktop or mobile systems. Nowadays manycore processors like Tilera TILE, KALRAY MPPA or Intel SCC combine a rising number of cores in a tiled architecture and are mainly designed for high performance applications with focus on direct inter-core communication. The current architectures have limitations by central or sparse components like memory controllers, memory I/O or inflexible memory management. In the future highly dynamic workloads with multiple concurrently running applications, changing I/O characteristics and a not predictable memory usage have to be utilized on these manycore systems.
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