Evaluation of a Hardware Implementation of the SVP Concurrency Model
SVP is a general concurrency model that has been implemented in the ISA of a multi-threaded core, both of which support data flow synchronization with imperative programming. This core is used as a building block to design System-on-Chips (SoCs) comprising many cores, either for general-purpose use or for specific applications. The major advantages of this implementation include asynchrony, i.e. the ability to tolerate long latency operations without impacting performance and the binary compatibility of programs when executed on an arbitrary number of cores.