Event-Driven Gate-Level Simulation with GP-GPUs

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely - from high-level descriptions down to gate-level ones - to validate several aspects of the design, particularly functional correctness. Despite development houses investing vast resources in the simulation task, particularly at the gate-level, it is still far from achieving the performance demands required to validate complex modern designs. In this paper, the authors propose the first event-driven logic simulator accelerated by a parallel, General-Purpose Graphics Processor Unit (GPGPU).
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