Expediating IP Lookups With Reduced Power Via TBM and SST Supernode Caching

Provided by: Reed Business Information
Topic: Hardware
Format: PDF
In this paper, the authors propose a novel supernode caching scheme to reduce IP lookup latencies and energy consumption in network processors. Instead of using an expensive TCAM based scheme, they implement a set-associative SRAM based cache. They use two different algorithms, Tree Bit-Map (TBM) and Shape Shifting Trie (SST), to organize an IP routing table as a supernode tree composed of a group of supernodes. They add a small supernode cache in-between the processor and the low-level memory containing the IP routing table in a tree structure.

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