Association for Computing Machinery
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using Chip Multi-Processors (CMPs) as the baseline to analyze problems in various domains. One of the main design issues facing CMP systems is the growing number of snoops required to maintain cache coherency and to support self/cross-modifying code that leads to power and performance limitations. In this paper, the authors analyze the internal and external snoop behavior in a CMP system and relax the snoopy cache coherence protocol based on the program semantics and properties of the shared variables for saving power.