Exploiting Eager Register Release in a Redundantly Multi-Threaded Processor

Provided by: The University of Tulsa
Topic: Hardware
Format: PDF
Due to shrinking transistor sizes and lower supply voltages, transient faults in computer systems are projected to increase by orders of magnitude. Fault detection and recovery can be achieved through redundancy. Redundant Multi-Threading (RMT) is one attractive approach to detect and recover from these errors. However, redundant threads can impose significant performance overheads by competing with the main program for resources such as the register file. In this paper, the authors propose using eager register release in the main program thread by exploiting the availability of register values in the trailing thread's register space.

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