Exploiting Local Logic Structures to Optimize Multi-Core SoC Floorplanning

Provided by: edaa
Topic: Hardware
Format: PDF
The authors present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of Latency-Insensitive (LI) systems. These two algorithms are integrated along with a published floor-planner in a new iterative physical synthesis flow to optimize system throughput and reduce area occupation. The partitioning algorithm performs bottom-up clustering of the internal logic of a given IP core to divide it into smaller ones, each of which has no combinational path from input to output and thus is legal for LI-interface encapsulation.

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