Provided by: Institute of Electrical & Electronic Engineers
Date Added: May 2014
Solid State Drives (SSDs) have been widely deployed in personal computers, data centers, and cloud storages. In order to improve performance, SSDs are usually constructed with a number of channels with each channel connecting to a number of NAND flash chips. Despite the rich parallelism offered by multiple channels and multiple chips per channel, recent studies show that the utilization of flash chips (i.e. the number of flash chips being accessed simultaneously) is seriously low. The authors' study shows that the low chip utilization is caused by the access conflict among I/O requests.