Institute of Electrical & Electronic Engineers
Shrinking integrated circuit feature sizes lead to increased variation and higher defect rates. This paper has shown how to tolerate the failure of entire LUTs and how to tolerate failures and high variation in interconnect. The authors show how to use Look-Up Tables (LUTs) even when they are partially defective - a form of fine-grained defect tolerance. They characterize the defect tolerance of a range of mapping strategies for defective LUTs, including LUT swapping in a cluster, input permutation, input polarity selection, defect-aware packing, and defect-aware placement.