Provided by: Institute of Electrical & Electronic Engineers
Date Added: Dec 2012
With shrinking transistor feature size, lowering nodal capacitance and supply voltage at new technology generations, microprocessors are becoming more vulnerable to single-event upsets and transients, a.k.a., soft errors. While Chip Multi-Processor (CMP) architecture has been employed in mainstream microprocessors and the number of on-chip processor cores keeps increasing, the system-level reliability of Chip Multi-Processors is degrading reversely proportional to the core number. In this paper, the authors propose to exploit abundant on-chip processor cores for redundant hardware transaction processing, which provides native support for error detection and recovery in Transactional Chip Multi-Processors (TxCMPs) against soft errors.